Cortex_M3 is a 32-bit processor core. The internal data path is 32 bits, the register is 32 bits, and the memory interface is 32 bits. CM3 adopts Harvard structure and has independent instruction bus and data bus, so that instruction fetching and data access can go hand in hand. In this way, data access no longer occupies the instruction bus, thus improving the performance. In order to realize this function, there are several bus interfaces in CM3, each of which is optimized for its own application, and they can work in parallel.

The characteristic of cortex-M3 architecture is that the processor core, data path, register and memory interface are all 32 bits. Using Harvard structure, data bus and instruction bus are independent, and instructions can be fetched and data can be read at the same time. Support big end mode and small end mode.