Complementary metal oxide semiconductor.
CISC (Complex Instruction Set Computing)
On board cache
On-chip cache
CPGA (ceramic pin grid array)
Central processing unit.
Embedded controller
Femms: enter/exit the multimedia state quickly, and enter/exit the multimedia state quickly.
First in first out: first in first out queue.
FPU: floating-point unit, floating-point arithmetic unit.
HL-PBGA: Surface adhesion, high heat resistance, light plastic spherical matrix package.
Ia: Intel architecture
Id: identifier, identification number
IMM: Intel Mobile Module, Intel Mobile Module
Kni (new instruction of Katmai, new instruction set of Katmai, namely MMX2)
MMX: Multimedia Extensions, Multimedia Extensions Instruction Set
Ni: Not Intel, not Intel.
PGA: Pin grid array (Pin grid array) consumes a lot of power.
PSN (processor serial number)
PIB: Boxed processor (Boxed processor)
PPGA (plastic pin grid array)
Plastic square flat package
Reduced instruction set computing
Seconds: Single-sided connector
SIMD: single instruction multiple data, single instruction multiple data
SiO2F (fluorinated silicon oxide).
SOI: silicon on insulator
SIMD stream extension.
TCP: Tape packaging (film packaging), low calorific value.
Translation observer buffer
Very long instruction word
Whql: Microsoft Windows Hardware Quality Lab (Microsoft Windows Hardware Quality Lab)
AGP: Accelerates the bus structure between graphics port, CPU and graphics chip.
Apic: advanced programmable interrupt controller (APIC)
Ball grid array (spherical grid array)
BTB/C: Branch Target Buffer/Cache (Branch Target Buffer)
CC: companion chip, motherboard chipset of MediaGX system.
Cisc: Complex Instruction Set Computing (Complex Instruction Structure)
Complementary metal oxide semiconductor (CMOS)
CP: Ceramic package (ceramic package)
CPGA: ceramic pin grid array (ceramic pin grid array)
Central processing unit (CPU)
DCT: Display Compression Technology (Display Compression Technology)
DIB: Dual independent buses, including L2cache bus and PTMM (processor to main memory) bus.
DP: dual processing (dual processor)
DX: refers to the CPU ECC: Error Check Correct (error checking and correcting) containing the math coprocessor.
ECRS: Entry calls the return stack and stores the return address instead of RAM.
Epic: Explicit parallel instruction computation is a 64-bit instruction set.
Floating point processing unit (floating point processing unit)
FRC: functional redundancy check (redundancy check, only dual processors have this function)
IA: Intel architecture (Intel architecture)
Input/output: input/output (input and output)
IS: internal stack (internal stack)
Iso/mpeg: moving picture expert group of international standard organization.
L 1cache: Level 1 (level 1) cache is usually integrated into the CPU, but there are also designs that integrate L2cache into the CPU, such as entity 2 lb:linear burst, which is a special technology adopted by Cyrix 6x86.
MADD: multiply-add instruction
MAG: Multiply-accumulate instruction, two floating-point numbers are multiplied and then added with another floating-point number, which can significantly improve the operation speed of 3D graphics.
MHz: megahertz, 1 GHz = 1000 MHz.
MIPS: Millions of instructions per second (millions of instructions per second) is a parameter of CPU speed. Of course, the bigger the better.
MMX: Multimedia extension (this should be familiar to everyone. This CPU has 57 new 64-bit instructions, which is the biggest change since 386, and SIMD architecture. )
MPGA: Micro PGA, which is smaller in heat dissipation and volume than TCP.
PGA: Pin Grid Array, which consumes a lot of power and is suitable for desktop computers.
Pin: CPU pin PLL: phase locked loop (PLL)
PR: P-rating is a rated performance index, based on Winstone 96 test (Winstone97 is used for PR2). For example, PR-75 is equivalent to Pentium 75 RISC: reduced instruction set computing, and is a ROB: Reorder Buffer relative to CISC.
SC: Static Core (Static Core)
SEC: unilateral contact is Intel's Pentium2CPU packaging box.
Slot 1: Pentium 2 main board structure, external bus frequency 66MHz.
Slot 2: Intel's next-generation chip socket, with local bus frequency exceeding 100MHz and larger SEC, is mainly used for servers, and can be installed with four CPU SMM (system management mode), which is an energy-saving mode.
Socket 7: Pentium CPU socket (classic Pentium and P55c) with external bus frequency of 83.3MHz.
Socket 8: the socket of high-energy Pentium CPU, with an external bus frequency of 66MHz SP: Scratch Pad (high-speed temporary storage).
SRR: segment register rewrite.
SRAM: SRAM Super 7: expansion slot 7, external bus frequency 100 MHz, AGP, L2/L3 cache, PC98, 100 MHz SDRAM.
SX: refers to a CPU without a mathematical coprocessor.
TCP: Tape packaging (film packaging), low calorific value, suitable for notebook computers.
TLB: translation look side buffer VMA: unified memory architecture. Vcc2 is used for system memory and display memory to provide voltage Vcc3(CLK) and voltage VLIW: very long instruction word (VRE): step-down enhancement (enhanced voltage regulation) of CPU input and output signals. VSA (Virtual System Architecture) writeback: It is a working mode of L 1cache. Direct writing: It is a working mode of L 1cache.
cpu
3DNow！ (3D without waiting)
arithmetic logic unit
AGU (address generation unit).
ball grid array
Branch prediction table
BPU (branch processing unit)
Transfer forecast (transfer forecast)
Complementary metal oxide semiconductor.
CISC (Complex Instruction Set Computing)
CLK (clock cycle)
On board cache
On-chip cache
CPGA (ceramic pin grid array)
cpu
Data Forwarding (data forwarding)
Decoding (instruction decoding)
Double independent bus
Embedded controller
Embedded chip (embedded)
Explicit explicitly parallel instruction code
FADD (floating point addition)
Flip-chip pin grid array
Floating point division
Femms: enter/exit the multimedia state quickly, and enter/exit the multimedia state quickly.
Fast Fourier transform
FID: frequency identification number
FIFO (first in, first out).
Flip-chip (chip inversion)
Floating-point operations per second
Floating point multiplication
Floating point unit
FSUB (floating point subtraction)
Universal visual processor
HL-PBGA: Surface adhesion, high heat resistance, light plastic spherical matrix package.
IA (Intel architecture)
Command control unit
Id: identifier, identification number
intel developer forum
IEU (integer execution unit)
IMM: Intel Mobile Module, Intel Mobile Module
cache memory
Instruction coloring (instruction classification)
Number of instructions per clock cycle
Instruction set architecture
KNI (Katmai new instruction set, Katmai new instruction set, SSE)
Incubation period (incubation period)
LDT (lightning data transmission).
Local interconnection (local interconnection)
Mesi (modify, exclusive, share, invalid: modify, exclude, * * * * enjoy, discard)
MMX (Multimedia Extension).
Multimedia unit
Mflops (millions of floating-point operations per second, millions of floating-point operations per second)
Megahertz (MHz)
Multiprocessing and multiprocessor architecture
Multiprocessor specification
Specific model register
NAOC (no account overclocking, invalid overclocking)
Ni: Not Intel, not Intel.
OLGA (organic land grid array)
OoO (fault)
PGA: Pin grid array (Pin grid array) consumes a lot of power.
Post RISC
Performance ratio
PSN (processor serial number)
Boxed processor
PPGA (plastic pin grid array)
Plastic square flat package
Original (write and read)
Register contents (register contention)
Registration pressure (insufficient registration)
Register renaming
Remarks (chip frequency relabeling)
Resource content (resource conflict)
Retirement (mandatory retirement)
Reduced instruction set computing
Seconds: Single-sided connector
Shallow trench isolation (shallow trench isolation)
SIMD (single instruction multiple data)
SiO2F (fluorinated silicon oxide).
System management interrupt
SMM (system management mode)
Symmetric multiprocessing.
SOI: silicon on insulator
SONC (system on chip)
System performance evaluation company
sqrt
SIMD stream extension.
Superscalar architecture
TCP: Tape packaging (film packaging), low calorific value.
Throughput (throughput)
TLB (translation observer buffer)
Uswc (non-cacheable speculative write combination).
vector arithmetic logic unit
Very long instruction word
VPU (vector permutation unit, vector permutation unit)
VPU (vector processing unit, processing SIMD instructions such as MMX and SSE).