With the development of the times, this mode of operation is facing greater challenges: in highly concurrent computing scenarios such as artificial intelligence, data transmission back and forth will generate huge power consumption; the current performance of the memory system lags behind that of the processor, and the limited memory bandwidth is unable to ensure high-speed data transmission.
December 3, fast technology was informed that the Dharma Institute successfully developed a new architecture chip. The chip is the world's first DRAM-based 3D bonded stacked storage-calculation integrated AI chip, which can break through the performance bottleneck of the von Neumann architecture and meet the demand for high bandwidth, high-capacity memory, and extreme arithmetic power in AI and other scenarios.
In specific AI scenarios, the chip improves performance by more than 10 times and energy efficiency by up to 300 times.
In the context of the gradual slowdown of Moore's Law, storage-computing integration has become a key technology to solve the performance bottleneck of computers.
All-in-one chip, similar to the human brain, integrates the data storage unit and the computing unit, dramatically reduces data handling, and thus greatly improves computing parallelism and energy efficiency.
This technology was proposed as early as the 1990s, but due to the complexity of the technology, the high design cost, and the lack of application scenarios, the industry has made slow progress in researching storage-computing chips over the past few decades.
The memory chip developed by Dharma Institute integrates several innovative technologies and is the world's first chip to use hybrid bonding 3D stacking technology to realize memory-computing integration. The chip's memory unit adopts heterogeneous integrated embedded DRAM (SeDRAM), which has the characteristics of ultra-large bandwidth and ultra-large capacity; in terms of the computing unit, Dharma Institute has developed and designed a streaming and customized gas pedal architecture, which accelerates the recommender system from "end to end", including the tasks of matching, coarse sorting, neural network computation, fine sorting, and so on.
With the help of a customized streaming accelerator architecture
Benefiting from the innovation of the overall architecture, the chip realizes both high performance and low system power consumption. In real-world recommendation system applications, compared with traditional CPU computing systems, the performance of the storage-computing integrated chip is improved by more than 10 times, and the energy efficiency is improved by more than 300 times. The research results of this technology have been included in ISSCC2022, the top conference in the chip field, and can be applied to VR/AR, unmanned driving, astronomical data computing, remote sensing image data analysis and other scenarios in the future.
Zheng Hongzhong, a scientist at the Dharma Institute's Computing Technology Laboratory, said, "Storage-computing integration is a disruptive chip technology, which naturally possesses the advantages of high performance, high bandwidth, and high energy-efficiency, and can solve the problems of chip performance and energy consumption in the post-Moore's Law era from the underlying architecture, and the chip developed by the Dharma Institute tightly integrates this technology with the scenarios, realizing the perfect fusion of memory, computing and the perfect integration of algorithmic applications."
It is reported that the Computing Technology Laboratory of Dharma Institute focuses on the research of chip design methodology and new computer architecture technology, and has a number of leading achievements, and has published many papers in top conferences such as ISSCC, ISCA, MICRO, HPCA, and so on.