In this data transfer bus converter, the FPGA is Xilinx's latest low-cost field programmable gate array, the Spartan-3E series of XC3S500E. XC3S500E contains 20 Block RAM, 18 KB of modular memory in each RAM block, which is a fully synchronized, true double-ended memory. The user can read from or write to each port independently (but the same address cannot be read and written to at the same time). In addition, each port has an independent clock, and the data width for each port can be configured independently.

The ARM chip selected is Samsung's S3C4510B. The S3C4510B is a cost-effective 16/32 bit RISC microcontroller for Ethernet-based applications, containing a 16/32 bit ARM7TDMI RISC processor core designed by ARM. In addition to the ARM7TDMI core, the S3C4510B has a number of important on-chip peripheral function modules, including an Ethernet controller for network communication between the S3C4510B system and other devices [1].

The DSP chip is selected from TI's TMS320C6416. TMS320C6416 is a high-speed fixed-point DSP from TI, which has a CPU with powerful processing capability, up to 1 MB of RAM, and a rich peripheral interface. Peripherals include CPU access to peripheral devices to provide a seamless interface to the flexible external memory interface EMIFA and EMIFB, a PCI interface that makes it easy for DSPs to seamlessly connect to an external host CPU with PCI functionality on the PCI interface, a 16/32 bit wide asynchronous parallel interface HPI (and PCI*** with the same pins), a provide 64 bit data channel access with enhanced EDMA, and so on. Its high-speed processing speed meets the system's real-time requirements and enables seamless connectivity with a wide range of peripherals.