Smartphone growth slowdown
Semiconductor downstream market drivers have gone through several phases, the first is the shipments of hundreds of millions of units of personal computers, and later become a billion units of cell phone terminals and communication products, and from 2010, smart phones as the representative of the smart mobile terminal set off the climax of the mobile Internet, becoming the latest killer application. Review of the previous two or three decades, the downstream electronics industry killer applications greatly stimulate the development of the semiconductor industry, and constantly incentivize semiconductor manufacturers to expand production capacity, improve performance, and with the semiconductor production enhancement, semiconductor prices will soon fall, cheaper and higher performance semiconductor devices and in turn promote the accelerated development of the electronics industry, the semiconductor industry and the electronics industry incentives for each other, the formation of a good positive feedback. But at the moment, the penetration rate of smartphones has been very high, the market growth rate began to slow down, the next killer application will be what?
IoT could be the next killer app
According to IHS, the number of IoT node connections will reach 70 billion in 2025.
In terms of volume, the IoT leaves the billion-dollar cell phone end-products far behind, and is likely to be the next wave of killer apps. But the problem with IoT is that the products are diverse and the applications are very decentralized. The market we are facing is changing from a single homogenized large-scale market to a small-scale heterogeneous market. For the semiconductor industry, which relies on volume, the chip design and flow of the chip is a huge investment in the early stage, no volume can not produce a scale effect, amortized to the cost of each chip is very high.
In addition to addressing the challenges of small-scale heterogeneity, IoT needs to have key elements including: diverse sensors (various types of sensors and Sensor Hub), distributed computing capabilities (cloud computing and edge computing), flexible connectivity (5G, WIFI, NB-IOT, Lora, Bluetooth, NFC, M2M, ...), and the ability to connect to the Internet of Things (IoT). ...), storage capabilities (memory and data centers) and network security. These key elements will stimulate the development of CPU/AP/GPU, SSD/Memory,biometric chips, wireless communication devices, sensors, memory devices and power devices.
IoT's diverse downstream product offerings put more demands on packaging
The diversity of IoT product offerings means that chip manufacturing will move away from purely pursuing process advancement to pursuing both process advancement and product line breadth. The likely trends for chips in the IoT era are: small package, high performance, low power, low cost, heterogeneous integration (Stacking, Double Side, EMI Shielding, Antenna...).
Packaging demand for automotive electronics: The current hotspot for automotive electronics is ADAS systems and driverless AI deep learning. The global automobile production and sales volume in 2016 was about 80 million units, of which 28 million units were produced and sold in the Chinese market, providing a large enough stage for automotive electronics.ADAS automotive systems have a broad development prospect, and for safety reasons, the U.S. NHTSA requires that automobiles produced from May 2018 onwards need to be mandatorily installed with a reversing image display system. In addition, the market for Lane Departure Warning System (LDW), Forward Collision Warning System (FCW), Automatic Emergency Braking System (AEBS), Vehicle Distance Control System (ACC), and Night Vision System (NV) is also growing rapidly. The increasingly stringent traffic regulations in China's first and second tier cities have also increased the demand for automotive electronic systems such as ADAS. ADAS, driverless, artificial intelligence, and deep learning require high real-time data processing, so the chip is required to achieve ultra-high computational performance, and there are also requirements for the miniaturization of the chip and the module design and heat dissipation, and the future of the automotive electronic chip may need to be used in the 2.5D technology for the integration of heterogeneity, such as the integration of the CPU, AEBS, ACC, and NV, which is a key component of the automotive electronic system. The future of automotive electronics chips may require heterogeneous integration using 2.5D technology, such as CPU, GPU, FPGA, and DRAM integration packages together.
Packaging requirements for personal mobile terminals: The personal consumer electronics market will continue to grow steadily, and the main demands of personal consumer electronics devices are miniaturization, power saving, high integration, low cost and modularity. For example, personal mobile terminals require the realization of a variety of functional modularity, the application processor module, baseband module, radio frequency module, fingerprint identification module, communication module, power management module, etc. integrated together. These products on the chip package form requirements are the same miniaturization, power saving, high integration, modularity, chip package form is mainly "Stack Die on Passive", "Antenna in SiP", "Double Side SiP", etc.. "Double Side SiP, etc. For example, Apple's 3D SiP integrated packaging technology, from the past ePOP & BD PoP, the development of the current is HBW-PoP and FO-PoP, the next generation of mobile terminal packaging form may be FO-PoP plus FO-MCM, this packaging form can provide a more ultra-thin design.
5G network chip packaging needs: 5G network and IoT-based NB-IOT network construction means that the network chip market will have a good performance. With the network closely Xiangguang big data, cloud computing and data centers, the demand for memory chips and FPGA GPU/CPU is very large. Communication network chips are characterized by large-scale, high-performance and low-power, in addition, intellectual property (IP) core complexity, yield and so on are important issues faced by vendors. These demands and issues have also led to the development of network chip packaging from Bumping & FC to 2.5D, FO-MCM, and 3D. while the successful commercialization of TSV technology has led to substantial progress in stacked packaging technology for chips, Hynix and Samsung have successfully developed High Bandwidth Memory (HBM) in 3D stacked packages, and Micron and Intel, among others, are jointly promoting Micron and Intel are also jointly promoting the research and development of stacked package hybrid memory cube (HMC). In the field of chip design, BROADCOM, GLOBAL FOUNDRIES and other companies have also successfully introduced TSV technology, and are now able to provide 2.5D stacked back-end design services for communication network chips.
Upstream Foundry Supply Side Impact on Packaging
On the one hand, the downstream market demand is very strong, and on the other hand, the capital led by large funds continues to invest heavily in the foundry manufacturing industry, so that the upstream manufacturing has been expanding capacity. According to SEMI estimates, the world will put into production between 2017 and 2020 62 semiconductor fabs, of which 26 in mainland China, accounting for 42% of the global total. Currently, fabs are still dominated by mature processes above 40
nm, accounting for 60% of the overall foundry output. In the future, automotive electronics, consumer electronics and network communications industries are demanding more and more chip integration, functionality and performance. Mainstream foundries SMIC and UMC are developing 28nm processes, of which TSMC's 28nm mass production has entered its fifth year and has even crossed over into the 10Xnm process.
As the wafer technology node continues to approach the atomic level, Moore's Law may be invalidated. How to continue Moore's Law? Instead of thinking only in terms of wafer fabrication, we should also think about the whole industrial chain from the whole process of chip fabrication, and need to optimize chip design, wafer fabrication, and packaging and testing at the system level. Therefore, the boundaries between wafer manufacturing, chip packaging and testing and system integration will become increasingly blurred. First of all, chip testing and system integration between the emergence of more and more subsystems, a variety of system-level packaging SiP needs to be different processes and functions of the chip, the use of 3D and other ways to package all together, not only to reduce the volume, but also to improve the ability to integrate the system Panel board-level packaging will also be a large-scale reduction in packaging costs, improve labor productivity. Secondly, fan-in and fan-out wafer-level packages have emerged between chip manufacturing and chip packaging, FO-WLP packages with ultra-thin, high I/O footage, is one of the third generation of packaging technology following the hit line, after the flip-flop, the final chip product has a small size, low cost, good heat dissipation, good electrical performance, high reliability and other advantages.
Advanced Packaging Development Status
Advanced packaging forms in the domestic application of more and more, the traditional TO and DIP package type of market share has been less than 20%,
In recent years, the industry's advanced packaging technology, including wafer-level packaging (WLCSP) and board-level packaging (PLP) as the representative of the 2.1D, 3D packaging, Fan Out WLP, WLCSP, SIP and TSV,
Before 2013, 2.5D TSV packaging technology was mainly applied to logic module integration, FPGA chip packaging and other products with a low level of integration. 2014, the industry's 3D TSV packaging technology has been partially applied to memory chips and high-performance chip packaging, such as high-capacity memory chip stacking, etc. In 2015, 2.5D TSV packaging technology was partially applied to memory chips and high-performance chip packaging, such as high-capacity memory chip stacking, and in 2015, the industry's 2.5D packaging technology was partially applied to memory chip stacking. In 2015, 2.5D TSV technology began to be applied to some high-end GPU/CPU, network chips, and processor (AP) + memory integrated chips. 3D packaging has more advantages in integration, performance, power consumption, smaller size, design freedom, development time, etc., and at the same time, design freedom is higher, development time is shorter, and it is a kind of the most promising development of each packaging technology. In the high-end cell phone chips, large-scale I/O chips and high-performance chips in a wide range of applications, such as an MCU plus a SiP, the original size reduced by 80%.
At present, the advanced packaging capabilities of leading domestic packaging and testing enterprises have been initially formed
Chairman Wang Xinchao of Changdian Technology, at the 2017 Semiconductor Packaging and Testing Annual Conference, for the current level of advanced packaging technology for China's sealing and testing vendors, also mentioned three points:
SiP System Level Packaging: At present, the highest level of integration and accuracy of the SiP module in Changdian Technology has achieved large-scale mass production; Huatian Technology has already realized large-scale mass production. has realized large-scale mass production; Huatian Technology's TSV + SiP fingerprint identification packaging products have been successfully applied to Huawei series of cell phones.
WLP Wafer Level Packaging (WLP): The cumulative shipments of Fan Out WLPs of Ever Tech have exceeded 1.5 billion pieces, and its wholly-owned subsidiary Ever Tech Advanced has become one of the world's largest IC Fan-In WLCSP packaging bases; and Crystal Power has become one of the world's largest WLP wafer level packaging bases for image sensors.
FC Flip Chip Packaging: Through cross-border mergers and acquisitions, leading domestic companies have gained access to international advanced FC Flip Chip Packaging technology, such as Changdian's FC-POP packaging technology for smartphone processors, and Tomfoolery's high pin-count FC-BGA packaging technology; the top three domestic packaging and testing factories have also basically mastered 16/14nm FC Flip Chip Packaging technology.