Memory tells how it works and what it does

Introduction

Memory (Memory) is a memory device used to save information in modern information technology. Its concept is very broad, there are many levels, in the digital system, as long as the binary data can be saved can be memory; in integrated circuits, a no physical form of the circuit with the function of storage is also called memory, such as RAM, FIFO, etc.; in the system, with the physical form of the storage device is also known as memory, such as memory strips, TF cards and so on. All information in the computer, including input raw data, computer programs, intermediate operation results and final operation results are stored in the memory. It deposits and removes information according to the location specified by the controller. With memory, the computer has a memory function to ensure normal operation. Computer memory according to the use of memory can be divided into main memory (memory) and auxiliary memory (external memory), also divided into external memory and internal memory classification method. External memory is usually magnetic media or CD-ROM, etc., can save information for a long time. Memory refers to the storage components on the motherboard, used to store data and programs currently being executed, but only for temporary storage of programs and data, turn off the power or power outage, the data will be lost.

The main function of the memory is to store the program and various data, and can be in the process of computer operation, high-speed, automatic program or data access. Memory is a device with a "memory" function, which uses physical devices with two stable states to store information. These devices are also called memory elements. In computers, data is represented in binary with only two digits, "0" and "1".

The two stable states of the memory element are represented as "0" and "1". Everyday decimal numbers must be converted to their binary equivalents before they can be stored in memory. Various characters handled in computers, such as the English alphabet and arithmetic symbols, must also be converted into binary code for storage and operation.

Memory: the device that stores the program and data storage bit: the storage unit that stores a binary digit is the smallest storage unit of the memory, or memory unit storage word: a number (n binary digits) as a whole when deposited or taken out, called the storage word storage unit: storage of a number of memory units of a storage word to form a storage unit storage unit storage unit storage unit: the collection of a large number of storage unit storage unit address. Storage unit address: the number of the storage unit word addressing: the storage unit by word addressing byte addressing: the storage unit by byte addressing addressing: from the address to find the data, from the corresponding address of the storage unit to access the data.

To the storage body (a large number of storage units composed of arrays) as the core, plus the necessary address decoding, read and write control circuits, that is, the storage IC; plus the necessary I / O interface and some additional circuits, such as access policy management, the formation of memory chips, such as cell phones commonly used in the memory chip. Thanks to the new IC manufacturing or chip packaging process, it is now possible to integrate DRAM and FLASH memory cells in a single chip. The memory chip is then integrated with the control chip (responsible for complex access control, storage management, encryption, cooperation with other devices, etc.) and clock, power and other necessary components on the circuit board to form a whole machine, is a storage product, such as a USB flash drive. From the storage unit (transistor array) to storage integrated circuits to storage devices, are to realize the storage of information, the difference is the level of different.

The storage medium that constitutes the memory, the storage element, which can store a binary code. A memory is composed of a number of storage elements, and then a memory is composed of many storage units. A memory contains many storage units, each of which can hold one byte (addressed by byte). The location of each storage unit has a number, i.e., an address, generally expressed in hexadecimal. The sum of the data that can be stored in all the storage units of a memory is called its storage capacity. Assuming that the address code of a memory consists of 20 binary digits (i.e., 5 hexadecimal digits), it can represent 2 to the 20th power, i.e., 1M memory cell addresses. Each memory cell holds one byte, so the memory has a storage capacity of 1MB.

Principle of operation

Only the principle of operation of dynamic memory (DRAM) is described here.

Dynamic memory has only one input data line per chip and only eight address pins. In order to form 64K addresses, an address formation circuit must be specially designed between the system address bus and the chip address leads. So that the system address bus signals can be added to the pins of the 8 addresses in time, with the help of the chip's internal row latch, column latch and decoder circuitry to select the memory cell in the chip, the latch signal also relies on the external address circuit to generate. When data is to be read from the DRAM chip, the CPU first adds the row address to A0-A7, and then sends out the RAS latch signal, the falling edge of which latches the address inside the chip. Next, the column address is added to A0-A7 of the chip, and then the CAS latch signal is sent, which also latches the column address inside the chip on the falling edge of the signal. Then keep WE=1, then the data is output and held during CAS validity.

When it is necessary to write data into the chip, the row and column addresses successively lock RAS and CAS inside the chip, then, WE is valid, plus the data to be written, then the data will be written into the selected storage unit. Because the capacitor can not be maintained for a long time charge unchanged, must be timed to the dynamic storage circuit of each storage unit to perform rereading operations to maintain a stable charge, this process is called dynamic memory refreshing. pc / XT machine in the DRAM refresh is realized using DMA. First the counter 1 of the programmable timer 8253 is applied to generate a DMA request every 1 careful 12 μs, which is added to channel 0 of the DMA controller. When the DMA controller 0 channel of the request is responded to, the DMA controller sends to refresh the address signal, the dynamic memory to perform a read operation, every read refresh line.

Main Role

Memory mainly stores programs and data. Just like a warehouse for storing goods, people usually number the goods in the warehouse in order to make it easier for them to be stored and accessed, and there is a way to store and access them.

Memory is composed of the storage body, address decoder, read/write control circuit, address bus and data bus. Can be directly accessed by the central processor random access instructions and data memory called main memory, disk, tape, CD-ROM and other mass memory called external memory (or auxiliary memory). Memory is the computer's memory device, its main function is to store the program and data. Programs are the basis of computer operation, data is the object of computer operation. Both programs and data are represented in memory in binary form and are collectively referred to as information. In the computer, memory capacity to byte (Byte, abbreviated as B) as the basic unit, a byte consists of eight binary bits (bit). In addition to the unit of storage capacity, there are KB, MB, GB, TB (can be abbreviated as K, M, G, T, for example, 128MB can be abbreviated as 128M). Where: 1KB = 1024B, 1MB = 1024KB, 1GB = 1024MB, 1TB = 1024GB. Memory is generally divided into main memory (memory) and auxiliary memory (external memory). The composition of the memory is shown in the figure. Random Access Memory (RAM) Main Memory (RAM) Read Only Memory (ROM) Memory Hard Disk Auxiliary Memory (External Memory) Floppy Disk CD-ROM Other Figure 1.1.2 Composition of the memory Main Memory and the CPU is directly connected to the storage of currently running programs and related data, access speed, but more expensive, the capacity can not be done too large, the current microcomputer's memory configuration is usually 128MB or 256MB; main memory (memory) is divided into random access memory (RAM) and read-only memory (ROM) according to the mode of operation; Random Access Memory (RAM) in the data can be randomly read or written, is used to store the program from the external memory into the program and the relevant data as well as the data sent from the CPU. People usually say that the memory actually refers to RAM.

Categorized by storage medium

(1) semiconductor memory memory composed of semiconductor devices known as semiconductor memory; features: high integration, large capacity, small size, fast access speed, low power consumption, inexpensive, simple maintenance. Mainly divided into two categories: bipolar memory: TTL type and ECL type. Metal Oxide Semiconductor Memory (referred to as MOS memory): static MOS memory and dynamic MOS memory.

(2)Magnetic surface memory made of magnetic material is called magnetic surface memory, referred to as magnetic memory. It includes disk memory, tape memory and so on. Characteristics: large size, low degree of automation, slow access speed, but the storage capacity is much larger than semiconductor memory and is not easy to lose.

(3) laser memory information in the form of engraved marks saved on the disk surface, with a laser beam irradiation disk surface, relying on the different reflectivity of the disk surface to read out the information. Optical disks can be divided into read-only optical disks (CD-ROM), write-once-only optical disks (WORM) and magnetic optical disks (MOD).

2. Classification by access method

(1) Random memory (RAM): If the content of any storage unit in the memory can be randomly accessed, and the access time is independent of the physical location of the storage unit, then this memory is called Random memory (RAM).RAM is mainly used to store a variety of input/output programs, data, intermediate arithmetic results, as well as store the information exchanged with the outside world and do stacking. RAM is mainly used to store various input/output programs, data, intermediate operation results, and information exchanged with the outside world and for stacking. Random memory is mainly used as cache memory and main memory.

(2) Serial Access Memory (SAS): If the memory can only be accessed in a certain order, that is, the access time is related to the physical location of the storage unit, the memory is called serial access memory. Serial memory can be further divided into sequential access memory (SAM) and direct access memory (DAM). Sequential access memory is completely serial access memory, such as magnetic tape, information in a sequential manner from the beginning of the storage medium to write (or read); direct access memory is part of the serial access memory, such as disk memory, which is between sequential access and random access.

(3) read-only memory (ROM): read-only memory is a kind of content can only read can not write memory, that is, a pre-written memory. Usually used to store fixed information. Such as often used as microprogram control memory. Currently there are rewritable read-only memory. Common mask ROM (MROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM).ROM circuitry than the RAM is simple, high integration, low cost, and is a non-volatile memory, computers are often some of the management, monitoring programs, mature user programs in the ROM.

3. According to the information of the preservation of classification

Non-permanent memory: power outages after the information disappears memory, such as semiconductor read/write memory RAM.

Permanent memory: power outages after the information can still be saved in the memory, such as magnetic materials made of memory and semiconductor ROM.

4. In the role of the computer system

Based on the role of memory in the computer system, can be divided into the main memory, auxiliary memory, cache memory, control memory and so on. In order to solve the memory requirements for large capacity, high speed, low cost of the contradiction between the three, is usually used in multi-level memory architecture, that is, the use of cache memory, main memory and external memory.

Capacity Impact

Operations such as switching from a write command to a read command, accessing an address at a certain time, and refreshing data require that the data bus remain at rest for a certain period of time, which does not fully utilize the memory channels. In addition, both wide parallel buses and DRAM core prefetching often result in unnecessarily large data accesses. The amount of useful data that can be accessed by the memory controller in a specified period of time is called the effective data rate, which depends greatly on the particular application of the system. The effective data rate varies over time and is often lower than the peak data rate. In some systems, the effective data rate can drop to less than 10 percent of the peak rate.

Often, these systems benefit from changes in memory technology that produce higher effective data rates. A similar phenomenon exists with CPUs, and in recent years companies such as AMD and TRANSMETA have pointed out that clock frequency is not the only factor in measuring the performance of CPU-based systems. Memory technology has matured to the point where peak rate and effective data rate may not be a better match than before. While peak rate remains one of the most important parameters of memory technology, other architectural parameters can greatly affect the performance of a memory system.

Parameters affecting the effective data rate

There are several types of parameters that affect the effective data rate, one of which is the stopping state that causes the data bus to enter a number of cycles. In this category of parameters, bus transitions, line cycle time, CAS delay, and RAS to CAS delay (tRCD) trigger most of the latency problems in the system architecture.

The bus transition itself creates very long stopping times on the data channel. In the case of a GDDR3 system, for example, the system is constantly writing data to the open pages of the memory. During this time, the memory system's effective data rate is comparable to its peak rate. However, assume that for 100 clock cycles, the memory controller transitions from read to write. Since this transition takes 6 clock cycles, the effective data rate drops to 94% of the peak rate. During these 100 clock cycles, more clock cycles would be lost if the memory controller switched the bus from write to read. This memory technology requires 15 idle cycles when switching from write to read, which further reduces the effective data rate to 79% of the peak rate. Table 1 shows similar calculations for several high-performance memory technologies.

Obviously, all memory technologies are not created equal. System designers who need a lot of bus transitions can boost performance by choosing more efficient technologies such as XDR, RDRAM, or DDR2. On the other hand, if the system can group processing transactions into very long read and write sequences, then bus transitions have the least impact on effective bandwidth. However, other increased latency phenomena, such as bank conflicts, can reduce the effective bandwidth and negatively impact performance.

DRAM technology requires that the pages or rows of a bank be open before they can be accessed. Once opened, different pages in the same bank cannot be opened until a minimum cycle time, known as the row cycle time (tRC), has elapsed. Accesses to different pages of a memory-open bank are called paging misses, which cause delays associated with any unmet portion of the tRC interval. For libraries that have not been opened for enough cycles to satisfy the tRC gap, paging omissions are called library conflicts. Whereas tRC determines the length of library conflict latency, the number of libraries available on a given DRAM directly affects how often library conflicts arise.

Most memory technologies have four or eight banks with tRC values over tens of clock cycles. Under random load, those cores with 8 libraries experience fewer library conflicts than those with 4 libraries. Although the interaction between tRC and the number of libraries is complex, its cumulative impact can be quantified in a number of ways.

Memory Read Transaction Processing

Consider three simple cases of memory read transaction processing. In the first case, the memory controller issues each transaction that creates a bank conflict with the previous transaction. The controller must wait a tRC time between opening a page and opening a subsequent page, which increases the maximum latency associated with the page loop. The effective data rate in this case is largely determined by the I/O and is largely limited by the DRAM core circuitry. The maximum library conflict frequency cuts the effective bandwidth to 20 to 30 percent of the current peak for the highest-end memory technologies.

In the second case, each transaction process targets a randomly generated address. At this point, the chance of generating a bank conflict depends on a number of factors, including the interaction between tRC and the number of libraries in the memory core. the smaller the tRC value, the faster the open pages cycle through, resulting in less loss of bank conflicts. In addition, the more libraries a memory technology has, the lower the chance of random address access library conflicts.

In the third case, each transaction is a page hit, addressing a different column address in the open page. The controller does not have to access the closed page, allowing full utilization of the bus, which gives an ideal situation where the effective data rate is equal to the peak rate.

Both the first and third cases involve simple computations, and the random case is affected by other features that are not included in the DRAM or memory interface. Memory controller arbitration and queuing would greatly improve the frequency of bank conflicts because it is more likely that there will be transaction processes that do not create conflicts rather than those that do.

However, increasing the memory queue depth does not necessarily increase the relative effective data rates between different memory technologies. For example, even with an increase in memory control queue depth, the effective data rate for XDR is 20% higher than GDDR3. This increment exists primarily because XDR has a higher number of banks and a lower tRC value. In general, shorter tRC intervals, more libraries, and larger controller queues yield higher effective bandwidth.

In fact, many of the efficiency-limiting phenomena are problems related to the granularity of row accesses. tRC constraints essentially require the memory controller to access a certain amount of data from newly opened rows to ensure that the data pipeline remains full. In fact, to keep the data bus running without interruption, only a very small amount of data must be read after opening a row, even if no additional data is needed.

The other major characteristic that reduces the effective bandwidth of a memory system is categorized as column access granularity, which specifies the amount of data that must be transferred for each read or write operation. In contrast, row access granularity specifies how many individual read and write operations are required for each row activation (generally referred to as CAS operations for each RAS). Column access granularity has a huge impact on the effective data rate that is not easily quantifiable. Because it specifies the minimum amount of data that needs to be transferred in a read or write operation, column access granularity creates problems for systems that require very little data at a time. For example, a 16-byte access granularity system that requires 8 bytes from each of two columns must read a total of ***32 bytes to access two locations. Because only 16 of the 32 bytes are needed, the effective data rate of the system is reduced to 50% of the peak rate. Two structural parameters, bus bandwidth and pulse time length, define the access granularity of the memory system.

Bus bandwidth is the number of data lines connecting the memory controller to the memory devices. It sets the minimum access granularity because for a given memory transaction, each data line must pass at least one data bit. The pulse time length, on the other hand, specifies the number of bits that must be passed per data line for a given transaction. A memory technique that passes only one data bit per data line per transaction has a pulse time length of 1. The total column access granularity is simple: column access granularity = bus width × pulse time length.

Many system architectures increase the available bandwidth of a storage system simply by increasing the DRAM device and storage bus bandwidth. After all, if four 400MHz data rate connections achieve a total peak bandwidth of 1.6GHz, then eight connections will yield 3.2GHz. adding a DRAM device increases the number of wires on the board and the number of pins in the ASIC, and the total peak bandwidth multiplies accordingly.

First and foremost, architects want to fully utilize the peak bandwidth, which is already the maximum they can achieve by physically designing the memory bus. It is not uncommon to see graphics controllers with 256-bit or even 512-bit memory buses that require 1,000 or more pins. Package designers, ASIC floor planners, and board design engineers can't find an inexpensive, commercially viable way to route this many signals across an area of silicon. Simply increasing the bus width to achieve higher peak data rates results in lower effective bandwidth due to column access granularity limitations.

Assuming that the pulse time length for a particular memory technology is equal to 1, a 512-bit wide system has an access granularity of 512 bits (or 64 bytes) for a memory process. If the controller only needs a small segment of data, the rest is wasted, which reduces the effective data rate of the system. For example, a controller that only needs to store 32 bytes of the system's data will waste the remaining 32 bytes, which in turn results in an effective data rate equal to 50% of the peak rate. These calculations assume a pulse time length of 1. With the trend toward increasing data rates for memory interfaces, most newer technologies have minimum pulse time lengths greater than 1.

Selection Tips

The type of memory will determine the operation and performance of the entire embedded system, so memory selection is a very important decision. Whether the system is battery-powered or utility-powered, the application requirements will determine the type of memory (volatile or non-volatile) and the purpose of use (storing code, data, or both). Also, the size and cost of the memory are important factors to consider in the selection process. For smaller systems, the memory that comes with the microcontroller is likely to fulfill the system requirements, while larger systems may require additional external memory. A number of design parameters need to be considered when selecting a memory type for an embedded system, including microcontroller selection, voltage range, battery life, read/write speed, memory size, memory characteristics, erase/write endurance, and total system cost.

Basic principles to follow when selecting memory

1. Internal vs. external memory

Generally, after determining the amount of storage space needed to store program code and data, the design engineer will decide whether to use internal or external memory. Typically, internal memory is the most cost-effective but least flexible, so the design engineer must determine if the need for storage will grow in the future and if there is some way to upgrade to a microcontroller with more code space. Based on cost considerations, it is common to choose the microcontroller with the least amount of memory to meet the application requirements, so special care must be taken when projecting code sizes, as increasing code sizes may require replacement of the microcontroller. External memory devices of various sizes exist on the market today, and it is easy to accommodate code size increases by adding more memory. Sometimes this means replacing existing memory with memory of the same package size but larger capacity, or adding memory to the bus. Even if the microcontroller comes with internal memory, the system's need for non-volatile memory can be met by adding external serial EEPROM or flash memory.

2, bootstrap memory

In larger microcontroller systems or processor-based systems, design engineers can use bootstrap code for initialization. The application itself usually determines whether boot code is needed and whether specialized boot memory is required. For example, if there is no external addressing bus or serial boot interface, internal memory is usually used without the need for a specialized boot device. However, in some systems without internal program memory, initialization is part of the operating code, so all code will reside in the same external program memory. Some microcontrollers have both internal memory and an external addressing bus, in which case the boot code will reside in the internal memory and the operating code in the external memory. This is likely to be the safest approach, since there is no chance of accidentally modifying the boot code when changing the opcode. In all cases, boot memory must be non-volatile memory.

Any type of memory can be used to meet the requirements of an embedded system, but the end-use application and total cost requirements are usually the main factors influencing our decisions. Sometimes a combination of several types of memory can be used to better meet the requirements of an application. For example, some PDA designs use both volatile and nonvolatile memories as program memory and data memory. Permanent programs are stored in nonvolatile ROM, while programs and data downloaded by the user are stored in battery-backed volatile DRAM. Regardless of which memory type is chosen, the design engineer must carefully compromise various design factors before determining the memory that will be used in the final application system.