Three, terminology
1. Computer system: consists of two major parts of the hardware and software, there are a variety of hierarchical structure.
2. Mainframe: CPU, memory and input/output interfaces together constitute the mainframe of the computer.
3. primary memory: used to store information that is being accessed
4. secondary memory: used to store information that is not being used temporarily.
5. Cache: used to store the paid copy of the information being accessed.
6. Central Processing Unit (CPU): the core component of a computer, consisting of an operator and a controller.
7. Hardware: refers to the physical part of the computer, which consists of visible and tangible various electronic components, various types of optical, electrical and mechanical equipment in kind.
Software: refers to the invisible and intangible, by the people pre-programmed with all kinds of special functions of the program components.
8. System software: also known as the system program, mainly used to manage the entire computer system, monitoring services, so that the system resources are reasonably scheduling, efficient operation.
Application software: also known as application programs, it is the user according to the task needs to prepare a variety of programs.
9. Source program: usually written by the user with a variety of programming languages.
Destination program: a machine language program that is translated by a computer into something that a machine can recognize.
10. Bus: is the information transmission line connecting multiple components, is the transmission medium for each component **** enjoy.
11. System bus: is the information transmission line between the major components of the CPU, main memory, I/O devices (through the I/O interface).
Communication bus: is the line used for communication between computer systems or between computer systems and other systems (such as control instruments, mobile communications).
According to the transmission method is divided into parallel and serial. Serial communication refers to the data in a single 1-bit wide transmission line, a one-by-one sequential time-sharing. Parallel communication means that data is transmitted simultaneously from source to destination on multiple parallel 1-bit wide transmission lines.
12. Bandwidth: The maximum amount of information that can be transmitted per unit of time.
13. Machine word length: is the number of bits of data processed by the CPU in parallel at one time, usually related to the number of register bits in the CPU.
14. Main memory capacity: is the total number of bits of binary code stored in the main memory.
15. Machine number: the sign bit is digitized, with 0 representing a positive number and 1 representing a negative number.
16. fixed-point number: a number in which the decimal point is fixed at a certain position.
17. Floating point numbers: numbers in which the position of the decimal point can float.
18. complementary code: one of the signed data representation, the inverse of the positive number and the original code is the same as the negative number of the inverse code is the binary inverted by bit in the lowest bit and then add 1.
19. overflow: in the computer, beyond the length of the machine word, the result of the occurrence of an error.
20. non-coding keyboard: a keyboard that uses software to determine whether a key is pressed and the method of setting the key, translating the key, and calculating the key value.
21. A/D converter: it can convert analog into digital, is the input device of the computer.
22. I/O interface: refers to the host and I/O devices set up between a hardware circuit and the corresponding software control.
23. Port: refers to some registers in the interface circuit, used to store data information, control information and status information.
24. Interrupt: the computer in the process of executing the program, when there is an abnormal situation or special request, the computer stops the operation of the current program to turn to these abnormalities or special requests to deal with the end of the process and then return to the current program interruptions to continue to execute the source program.
25. Interrupt source: All the factors that can make interrupt requests to the CPU are collectively called interrupt sources.
26. Interrupt nesting: computer in the process of processing interrupts, there may be a new interrupt request, at this time the CPU to suspend the current interrupt service program, turn to the new interrupt request, this phenomenon is called interrupt nesting.
27. Priority: In order to enable the system to respond in a timely manner and deal with all the interruptions that occur, the system according to the importance of causing interruptions and the degree of urgency of the event, the hardware will be divided into a number of levels of interrupt sources.
28. DMA mode: hardware is used to transfer data directly between the main memory and the peripherals without the need of CPU, controlled by software.
29. Instruction system: The collection of all machine instructions is called the instruction system of the machine.
30. Addressing: refers to the method of determining the data address of this instruction and the address of the next instruction to be executed, which is closely related to the hardware structure, and directly affects the format and function of the instruction.
31. Instruction cycle: the time to complete an instruction, consisting of a number of machine cycles.
Machine cycle: the completion of touching a separate operation, consisting of a number of clock cycles.
Clock cycle: the most basic unit of time, determined by the main frequency.
32. Micro-operation: In a microprogram controller, the most basic operation performed by an executing part after receiving micro-instructions.
33. Microinstruction: the control code stored by the controller, which is divided into the operation control part and the sequence control part, and consists of microcommands.
34. Microprogram: the program stored in the control memory to complete the function of the instruction, consisting of micro-instructions.
35. control memory: read-only memory in the CPU used to store the microprograms that implement all the instructions of the instruction system.
II. Calculation
3.14. Let the clock frequency of the bus be 8 MHZ and one bus cycle is equal to one clock cycle. If 16 bits of data are transmitted in parallel in one bus cycle, what is the bandwidth of the bus?
Solution: Since: f=8MHz,T=1/f=1/8M sec because one bus cycle is equal to one clock cycle
So: Bus bandwidth = 16/(1/8M) = 128Mbps=16MBps
3.15. In a 32-bit bus system, the clock frequency of the bus is 66MHZ, and assuming that bus In a 32-bit bus system, the clock frequency of the bus is 66 MHZ. Assuming that the shortest transmission period of the bus is 4 clock cycles, calculate the maximum data transfer rate of the bus. What measures can be taken to increase the data transfer rate?
Solution: Bus transfer period = 4*1/66M seconds
Maximum data rate of the bus = 32/(4/66M)=528Mbps=66MBps
To increase the data rate, you can either increase the bus clock frequency, increase the width of the bus, or reduce the number of clock cycles in the bus transfer period.
3.16. In an asynchronous serial transmission system, the character format is: 1 start bit, 8 data bits, 1 check bit, and 2 termination bits. If 120 characters per second are required to be transmitted, find the baud rate and bit rate of the transmission.
Solution: A frame contains: 1+8+1+2=12 bits
Therefore, the baud rate is: (1+8+1+2)*120=1440bps
The bit rate is: 8*120=960bps
4.5. What is the bandwidth of memory? If the data bus width of the memory is 32 bits and the access cycle is 200ns, what is the bandwidth of the memory?
Solution: The bandwidth of a memory refers to the maximum amount of information going in and out of the memory per unit of time.
Memory bandwidth = 1/200ns × 32 bits = 160M bits/sec = 20MB/sec (Note: 1ns = 10-9s)
4.7. What is the sum of the address and data lines of a memory with a capacity of 16K × 32 bits? How many pieces of each of the following memory chips of different sizes are required when selected?
1K x 4-bit, 2K x 8-bit, 4K x 4-bit, 16K x 1-bit, 4K x 8-bit, 8K x 8-bit
Solution: sum of address and data lines = 14 + 32 = 46;
The number of slices required for each of the different chips when they are selected is:
1K x 4: (16K x 32) / (1K x 4) = 16 x 8 = 128 chips
2K×8: (16K×32) / (2K×8) = 8×4 = 32 chips
4K×4: (16K×32) / (4K×4) = 4×8 = 32 chips
16K×1: (16K×32) / (16K×1) = 1×32 = 32 chips
4K×8: (16K×32) / (4K×8) = 1×32 = 32 chips
4K×8: (16K×32) / (4K×8) = 1×32 = 32 chips
4K×8: (16K×32) / (4K×8) = 4×32 = 32 chips 32) / (4K×8) = 4×4 = 16 slices
8K×8: (16K×32) / (8K×8) = 2×4 = 8 slices
6.4. Given that the length of the machine digit is 8 bits (including 1 sign bit), write the original, complement and inverse codes corresponding to each of the following truth values. -13/64, -87
Solution: the truth values correspond to the different machine codes as follows:
Truth value -13/64 -87
Original code 1.001 1010 1, 101 0111
Supplement 1.1100110 1, 0101001
Inverse code 1.1100101 1. 0101000
6.5. Knowing the [x]-complement, find the [x]-original sum x.
[x1]-complement = 1,1100; [x2]-complement = 1,1001; [x4]-complement = 1,0000;
[x5]-complement = 1,0101; [x6]-complement = 1,1100; [x8]-complement = 1,0000;
Solve: [x5]-complement = 1,0101; [x6]-complement = 1,1100; [x8]-complement = 1,0000;
Solutions. p>Solution: [x]complement corresponds to [x]original and x as follows:
True value -1/4 -7/16 -1 -11 -4 -16
[x]complement 1.1100 1.1001 1.0000 1,0101 1,1100 1,0000
[x]original 1.0100 1.0111 none 1,1011 1, 0100 None
x -0.0100 -0.0111 -1.0000 -1011 -0100 -10000
6.9. When the hexadecimal numbers 9B and FF are expressed as the original, complement, inverse, shifted, and unsigned numbers, respectively, what are the corresponding decimal numbers (given that the machine numbers use one sign bit)?
Solution: The correspondence between the truth value and the machine number is as follows:
Original Complement Shifted Unsigned
9BH -27 -101 +27 155
Original Complement Shifted Unsigned
FFH -128 -1 +128 256
6.12. The format of a floating-point number is given as follows: ordinal 5 bits (including 1 bit of the ordinal), mantissa 11 bits, and mantissa 11 bits. bit order character) and 11 bits in the mantissa (with 1 bit digit character). Write the machine numbers corresponding to -27/1024, -86.5. The requirements are as follows:
(1) Both the order code and the mantissa are original.
(2) Both the ordinal and the mantissa are complementary.
(3) The order code is shifted and the tails are complementary.
Solution: Draw the format of this floating point number according to the question:
1 digit of order code 4 digits of degree code 1 digit of number code 10 digits of mantissa
Converting the decimal number to binary: x1= -27/1024= -0.0000011011B = 2-5*(-0.11011B)
x3=-86.5=- 1010110.1B = 27*(-0.10101101B)
The floating-point specification numbers for each of the above are:
(1) [x1] original = 1, 0101; 1.110 110 000 0
[x3] original = 0, 0111; 1.101 011 010 0
(2) [x1] Complement = 1, 1011; 1.001 010 000 0
[x3] Complement = 0, 0111; 1.010 100 110 0
(3) [x1] Shift Complement = 0, 1011; 1.001 010 000 0
[x3] Shift Complement = 1, 0111; 1.010 100 110 0
6.19. Given that the machine digit is 8 bits long (including 1 sign bit), compute each of the following using the complement arithmetic rule.
(2) A=19/32, B= -17/128, find A-B.
(4) A= -87, B=53, find A-B.
Solution: (2) A=19/32= 0.100 1100B, B= -17/128= -0.001 0001B
[A]'s complement = 00.100 1100, [B]-complement = 11.110 1111 , [-B]-complement = 00.001 0001
[A-B]-complement = [A]-complement + [-B]-complement
= 00.1001100 + 00.0010001
= 00.1011101 - -no overflow
A-B= 0.101 1101B = 93/128B
(4) A= -87= -101 0111B, B=53=110 101B
[A]-complement=11, 010 1001, [B]-complement=00, 011 0101, [-B]-complement=11 , 100 1011
[A-B]-complement = [A]-complement + [-B]-complement
= 11,0101001 + 11,1001011
= 10,1110100 -- an overflow
6.21. Add, subtract, alternate, and complement with primitive code Calculate x ÷ y by the alternating method of addition and subtraction.
(2) x = -0.10101, y = 0.11011;
(4) x = 13/32, y = -27/32.
(2) [x] original = 1.10101 x* = 0.10101 [X*] complement = 1.01011 Xf?Yf=1
0.10101
+1.00101
1.11010 0
1.10100
+0.11011
0.01111 0
0.11110
+1.00101
0.00011 011
0.00110
+1.00101
1.01011 0110
0.10110
+0.11011
1.10001 01100
1.00010
+0.11011
1.11101 011000
[y] original = 0.11011 y* = 0.11011 [Y*] complement = 0.11011 [-y*] complement = 1.00101
[x/y] original = 1.11000
(4) do the same thing, it is too tiresome to type the table, just give the result. [x/y] originally = 1.01111
Three applications
4.14. An 8-bit microcomputer with an 18-bit address code, if you use a 4K x 4-bit RAM chip to form a module-board structure of the memory, ask:
(1) What is the maximum amount of main memory space allowed for this machine?
(2) If each module board is 32K x 8 bits, *** how many module boards are needed?
(3) How many RAM chips are **** inside each module board?
(4) How many RAM chips does **** have?
(5) How does the CPU select each module board?
Solution: (1) The maximum main memory space allowed in the machine is: 218 × 8 bits = 256K × 8 bits = 256KB
(2) Total number of module boards = 256K × 8 / 32K × 8 = 8
(3) Number of chips in the boards = 32K × 8 bits / 4K × 4 bits = 8 × 2 = 16 chips
(4) Total number of chips = 16 × 8 = 128 pieces
(5) The CPU selects the template through the highest 3-bit address decoder output, and the next highest 3-bit address decoder output selects the chip. The address format is assigned as follows:
4.29. Assuming that the CPU executes a certain program *** access to the Cache hits 4800 times, access to the main memory 200 times, known as the Cache access cycle is 30ns, the main memory access cycle is 150ns, find the Cache hit rate as well as the average access time and efficiency of the Cache-main memory system, and ask how many times the performance of the system has been improved. How many times has the performance of the system improved?
Solution: Cache hit rate is 4800/(4800+200)=24/25=96%
The average access time of the Cache-main memory system is ta=0.96*30ns+(1-0.96)*150ns=34.8ns
The access efficiency of the Cache-main memory system is: e=tc/(1-0.96)*150ns
Access efficiency of the Cache-main memory system is is: e=tc/ta*100%=30/34.8*100%=86.2%
The performance is 150ns/34.8ns=4.31 times the original, i.e., 3.31 times better.
Example 7.2 Let the transfer instruction for relative addressing take up 3 bytes, the first byte is the opcode, and the second and third bytes are the relative displacements (complementary code representation). And the data is stored in the memory using the low byte address as the word address. Whenever the CPU removes a byte from the memory, it automatically completes (PC) +1 PC.
(1) If the current value of PC is 240 (decimal), and it is required to be transferred to 290 (decimal), what is the machine code for the second and third bytes of the transfer instruction?
(2) If the current value of PC is 240 (decimal) and a transfer to 200 (decimal) is requested, what are the machine codes for the second and third bytes of the transfer instruction?
Solution: (1) the current value of PC is 240, the PC value is 243 after the instruction is taken out, and it is required to be transferred to 290, i.e., the relative displacement is 290-243=47, which is converted to 2FH. Since the data is stored in the memory in the way of word address with the low byte address, the second byte of the transfer instruction is 2FH and the third byte is 00H.
< p>(2) The current value of PC is 240, and the value of PC is 243 after the instruction is taken out, which is required to be transferred to 200, i.e., the relative displacement is 200-243=-43, which is converted into the complement of D5H. Since the data is stored in the memory with the low byte address as the word address, the second byte of the transfer instruction is D5H, and the third byte is FFH.
Example 7.3 A double-word-length directly addressed subroutine call instruction, the first word of which is the opcode drink addressing feature, and the second word is the address code 5000H. Suppose the current value of PC is 2000H, the content of SP is 0100H, the top of the stack is 2746H, the memory is addressed by byte, and the operation into the stack is performed by executing (SP) - △ - P, after which the data is deposited. What are the PC, SP and top-of-stack contents in each of the following cases?
(1) Before the CALL instruction is read.
(2) After the CALL instruction is executed.
(3) After the subroutine returns.
Before solving CALL instruction is read, PC=2000H, SP=0100H, the top of stack is 2746H.
(1) After CALL instruction is executed, hesitation memory is compiled according to byte, CALL instruction is supplied to account for 4 bytes, so the program breaks the power of 2004H to enter the stack, at this time, SP=(SP)-2=00FEH, the top of stack content is 2004H, PC is updated to the subroutine entry address 5000H.
(2) After the subroutine returns, the program breaks out of the stack, PC=2004H, SP is modified to 0100H, and the content of the top of the stack is 2746H.
7.6 The word length of a certain instruction system is 16 bits, and the address code is taken to be 4 bits, so try to put forward a program to make the address system have 8 triple address instructions, 16 two-address instructions, and 100 one-address instructions.
Solution:
OP A2 A1 A0 8 triple-address instructions
0000
0111
OP A1 A0 16 second-address instructions
10000000
10001111
10001111
10001111 p>
OP A0 one-address instructions 100
110000000000
110001100011
7.7 Let the instruction word length be 16 bits, and use the extended opcode technique, where the address of each opcode is 6 bits. If 13 two-address instructions are defined, ask how many more one-address instructions can be arranged.
Solution: (24-3)*26=3*64=192 instructions
7.8 The instruction word length of a certain machine is 16 bits, and the address code of each operand is 6 bits. Given that the length of the opcode is fixed, and the instructions are categorized into three types of formats: zero-address, one-address, and two-address, how many at most two-address instructions can be defined, if there are M kinds of zero-address instructions and N kinds of to-address instructions? If the number of operand bits is variable, how many two-address instructions are allowed at most?
Solution: 1) If fixed-length opcodes are used, the format of second-address instructions is as follows:
OP (4 bits) A1 (6 bits) A2 (6 bits)
There are K kinds of second-address instructions, then: K=24-M-N
When M=1 (minimum), N=1 (minimum), there are at most: Kmax=16-1-1 = 14 kinds
2) If the variable-length opcode is used, the two-address instruction format is still as shown in 1), but the length of the opcode can vary with the number of address codes. In this case, K= 24 - (N/26 + M/212 );
When (N/26 + M/212 )?1 (N/26 + M/212 upward rounding), K is the largest, then there are at most two-address instructions:
Kmax=16-1=15 kinds of (only one code is left to be used as an extension flag.)
9.5 Given that the CPU frequency of machine A is 8 MHz, the machine cycle is 4 clock cycles, and the average instruction execution speed of the machine is 0.4 MIPS, find the average instruction cycle and the machine cycle of the machine, and how many machine cycles are contained in each instruction cycle? If the CPU frequency of machine B is 12MHz and the machine cycle also contains 4 clock cycles, try to find the average instruction execution speed of machine B is how many MIPS?
A.CLK=8MHz T=1/8MHz=0.125us
Machine cycle=4*T=0.5us
Because the execution speed is 0.4MIPS So average instruction cycle = 1/0.4MIPS = 2.5us
2.5us/0.5us = 5 So each instruction contains 5 machine instructions
B.T=1/f=1/12MHz=1/12us Machine instruction = 4*T=1/3us Instruction cycle = 5*1/3=5/3us
Average instruction execution speed 1/(5/3)=0.6MIPS
9.6 If the CPU frequency of a computer is 8MHz, each machine cycle contains 2 clock cycles on average, and each instruction has 4 machine cycles on average, how many MIPS is the average instruction execution speed of this computer? If the CPU frequency remains unchanged but each machine cycle contains 4 clock cycles on average, and each instruction has 4 machine cycles on average, how many MIPS is the average instruction execution speed of this computer? There are 4 machine cycles on average, how many MIPS is the average instruction execution speed of machine B?
1.CLK=8MHz Average instruction execution speed 1/(1/8M*2*4)=1MIPS
2.Instruction cycle=4*4*1/8=2us Execution speed=1/(1/8M*4*4)=0.5MIPS
9.7 The main frequency of a CPU is 10MHz, if it is known that each machine cycle contains 4 clock cycles on average, the average instruction execution speed of this machine is 1MIPS, try to find out the average instruction execution speed of this machine is how many MIPS?If the main frequency of the CUP remains unchanged, but each machine cycle contains 4 clock cycles on average, and each instruction has 4 machine cycles on average, the average instruction execution speed of this machine is how many MIPS? And how many MIPS?What can be concluded from this
1.Average Instruction Cycle=1/1MIPS=1us T=1/f=0.1us T Machine=4*T=0.4us
Because 1us/0.4us=2.5 so each instruction contains 2.5 machine cycles
2.T=0.4us Speed=1/( 0.4*2.5*4)=0.25MIPS
3. Since speed=0.8MIPS so T finger=1/0.8us
Since T finger=4*2.5*T so T=1/8us so f=1/T=8MHz
Four, Short Answer
1. Main features of Von Neumann machine mainframe.
○1 A computer consists of five major components: operator, memory, controller, input device and output device.
○2.Instructions and data are stored together in memory in equal positions and can be sought by address.
○3. Instructions and data are expressed in binary.
○4. Instructions consist of an operation code and an address code, which is used to indicate the nature of the operation, and an address code, which is used to indicate the location of the operand in the memory.
○5. Using the principle of memory control, instructions are stored sequentially in memory. Normally, instructions are executed sequentially, but under certain conditions, the order of execution can be changed based on the results of operations or according to set conditions.
○6. The machine is centered on an operator, and the data legend between the input and output devices and the memory is done through the operator.
2. Main technical specifications of computer hardware, software definition and classification.
The main technical indicators of computer hardware: machine word length, storage capacity, computing speed, main frequency.
Definition of software: invisible and intangible, composed of pre-programmed programs with various types of special functions.
Classification: system software and application software.
3. Computer components and the role of individual parts.
Operator: Used to complete arithmetic and logical operations, and the intermediate results of the operations are stored temporarily in the operator.
Memory: used to store data and programs.
Controller: used to control, command the program and data input, operation, and processor results.
Input devices: used to convert familiar forms of information into forms of information that can be recognized by the machine, common keyboard, mouse, etc..
Output devices: the results of machine operations can be converted to familiar forms of information, such as printer output, monitor output.
4. Bus definition and classification methods, system bus definition and classification methods.
Bus
Definition: A bus is an information transmission line that connects multiple components, and is the transmission medium that each component **** enjoys.
Classification: On-chip bus System bus Communication bus
System bus
Definition: A system bus is an information transmission line between major components of the CPU, main memory, and I/O devices (via I/O interfaces).
Classification: Data bus Address bus Control bus
5. What is a bus standard and what are the current popular bus standards.
The so-called bus standards can be seen as a standard interface for interconnecting the system with each module, and the modules with each other.
ISA bus, EISA bus, PCI bus, RS-232C bus, IEEE-488 (parallel communication bus also known as GP-IP bus) USB bus.
6. What are the characteristics and uses of each level of memory in a three-level memory system, and what are the two levels.
○1 Main memory Characteristics: random access, fast speed. Large capacity. Purpose: Holds programs and data used by the CPU.
Secondary memory Characteristics: large capacity, slow, low price, can store information offline. Purpose: to store a large amount of backup data
Cache Features: fast, small capacity, high price Purpose: used as a buffer between the main memory and the auxiliary memory, being used to pay for the program and data.
○2 Cache ----- main memory level and main memory - auxiliary village level.
7. Semiconductor memory RAM and ROM characteristics and uses.
RAM characteristics: readable and writable information loss after power-down, storage of temporary information. Usage: mainly used as memory
ROM characteristics: read only, not write after power failure information is not lost, store long-term information. Usage: Mainly used as control memory
8. Dynamic RAM and static RAM features and uses, DRAM refresh method and main advantages.
Static RAM features: after the information is read out, it still maintains its original state and does not need to be regenerated. Usage: Used in Cache
Dynamic RAM characteristics: rely on the principle of capacitive storage charge to host information. Usage: Composed of memory/main memory.
DRAM refresh method
Centralized refresh: Centralized refresh is a specified refresh cycle for all memory cells to concentrate on a period of time to refresh line by line, at this moment must stop reading and writing operations.
Decentralized refresh: Decentralized refresh means that the refresh of each row of storage units is spread over each storage cycle.
Asynchronous refresh: Asynchronous refresh is a combination of the first two ways, it can shorten the "dead time", but also take full advantage of the maximum refresh interval of 2ms.
Advantages: a single MOS tube, high integration, slower than SRAM, low price,
9. Cache working principle characteristics, address mapping and replacement algorithm.
Principle: the use of program access to the local nature of the recent use of information stored in the cache.
Address mapping methods: direct mapping, full-phase mapping, group-phase mapping,
Replacement algorithms: first-in, first-out algorithm (FIFO), the recent least-used algorithm (LRU), the random method.
10. Host and peripheral exchange of information using interrupt and DMA method characteristics and applications.
Interrupt mode:
Features: CPU and peripherals work in parallel, high efficiency
Applications: management of a variety of peripherals work in parallel, real-time processing, automatic fault handling
DMA mode:
Features:
○1 From the point of view of the data transfer, the program interrupt mode relies on the program to transfer, DMA mode relies on the hardware to transfer. DMA mode relies on hardware transmission.
2From the CPU response time, the program interrupt method responds at the end of the execution of an instruction, while the DMA method responds at the end of any access cycle within an instruction cycle.
○3The program interrupt method has the ability to handle abnormal events, while the DMA method does not. It is mainly used for bulk data transfer, such as hard disk access, image processing, and high-speed data acquisition systems, to improve data throughput.
<4>The program interrupt method needs to interrupt the current program, so it is necessary to protect the site; the DMA method does not interrupt the current program, so it is not necessary to protect the site.
The priority of DMA is higher than that of program interrupt.
Applications: high-speed devices such as hard disk
11. Difference between I/O ports and interfaces, and classification of I/O interfaces.
Port: The internal registers of the interface have I/O address numbers. They are generally categorized as data, command and status ports.
Interface: a number of ports plus the corresponding control circuitry composition.
Interface classification: serial interface and parallel interface according to the data transfer mode
According to the flexibility of the function selection is divided into programmable interface and non-programmable interface
According to the generality of the interface is divided into general-purpose interfaces and special interfaces
According to the control mode of the data transfer is divided into the program-type interface and the DMA interface.
12. interrupt processing process is divided into which two phases what tasks are accomplished
response phase: turn off the interrupt, protect the breakpoint address, go to the interrupt service entry address
processing phase: protection of the scene, the execution of the user-written interrupt service program, restoration of the scene.
13. What are the main features of the MDA method compared to the interrupt method.
○1 In terms of data transfer, program interrupt method relies on program transfer and DMA method relies on hardware transfer.
○2 In terms of CPU response time, the program interrupt method responds at the end of the execution of an instruction, while the DMA method can respond at the end of any access cycle within an instruction cycle.
○3The program interrupt method has the ability to handle abnormal events, while the DMA method does not. It is mainly used for bulk data transfer, such as hard disk access, image processing, and high-speed data acquisition systems, to improve data throughput.
<4>The program interrupt method needs to interrupt the current program, so it is necessary to protect the site; the DMA method does not interrupt the current program, so it is not necessary to protect the site.
The priority of DMA is higher than that of program interrupt.
14. What is addressing mode and what are the types of data addressing modes.
Addressing method: It is the method of determining the data address of this instruction and the address of the next instruction to be executed, which is closely related to the hardware structure and directly affects the instruction format and instruction function.
Data addressing: immediate addressing, direct addressing, implicit addressing, indirect addressing, register addressing, register indirect addressing, base addressing, variable addressing, relative addressing, stack addressing.
15.RISC main features compared to CISC RISC main advantages.
Features:
Selection of some simple instructions that are used more frequently and some very useful but not complex instructions, so that the functions of complex instructions are realized by a combination of simple instructions with high frequency;
Fixed instruction length, fewer types of instruction formats, fewer types of addressing modes;
Only fetch/store instructions access memory, and the rest of the instructions are done in registers;
Only fetch/store instructions access memory. The rest of the instruction operations are done in registers;
Using pipeline technology, most of the instructions are done in one clock cycle;
The controller is controlled by combinational logic, not by microprograms;
Using the optimized compilation program.
○1 Fully utilize the area of the VLSI chip.
○2 Increase the speed of computer operations.
○3 Easy to design can reduce cost and improve reliability.
○4Effective support for high-level language programs.
16. Combinatorial logic and microprogramming main features and applications.
Combinational logic: characteristics: fast, complex and inflexible. Applications: for RISC machines.
Micro-programming: characteristics: the introduction of programming and storage logic technology, hardware softening, a machine instruction with a piece of microprogramming, stored in the control memory CM. Application: series of machines.
17. What is instruction cycle, machine cycle, clock cycle How are the three related.
Instruction cycle: the time to complete an instruction, consisting of a number of machine cycles.
Machine cycle: the time to complete the touch of a separate operation, consisting of a number of clock cycles.
Clock cycle: the most basic unit of time, determined by the main frequency.
Relationship: clock cycle is the most basic unit of time, composed of a number of clock cycles to form the machine cycle, composed of a number of machine cycles to form the instruction cycle.